As is known, dynamic performance at radio frequencies of an active device is frequently penalized by the presence of undesirable parasitic elements that arise from the particular technique employed for implementation. Frequently, performance is limited by regions of the device that are not really active but are indispensable for its fabrication. For example, contact pads, which are necessary for connecting the device to the pins of the package, have reactive components that dissipate towards the substrate, which can affect the integrity of the radio-frequency electrical signal. The same reasoning applies to all the power metallic interconnections connecting a multitude of active regions to one another in order to provide a single power device. These connections can reach lengths of several hundreds of micron and consequently, as the working frequency rises, can manifest, in addition to resistive characteristics, inductive and capacitive components.
In other words, when the dynamic characteristics of an integrated electronic device are to be assessed, it is necessary to evaluate both the characteristics due to the intrinsic active part, which constitutes the very heart of the device, and the ones due to the extrinsic part that performs the accessory functions.
It is moreover known that lateral power MOS devices can be advantageously employed from frequencies of some hundreds of MHz up to frequencies of a few GHz, with power values that range from a few watts to some hundreds of watts. In order to reach the considerable power values required, these devices are normally obtained by parallel connecting a large number of elementary MOS devices. The parasitic elements introduced by the interconnections consequently play an important role and have been dealt with and solved in different ways.
For example, U.S. Pat. No. 5,252,848 describes a structure where, in order to minimize the parasitic capacitance between the gate electrode and the drain electrode, a conductive layer is provided that extends both on top of the gate and at the side thereof, towards the drain and source electrodes.
For the conductive shield to be effective, it should be connected to ground, and its vertical distance from the drain region, formed within the substrate, should be small and in the region of 100-200 nm.
In this patent then, on the one hand, the shield is prolonged laterally as far as the source electrode and is electrically connected thereto; on the other hand, it suggests choosing the thickness of the dielectric arranged between the shield and the drain region, formed within the substrate, as small as possible. However, with this geometry, it is difficult to reduce the distance of the shield from the drain region because, by so doing, the vertical distance between the portion of the shield overlying the gate and the gate would also decrease. Consequently, the parasitic capacitance between gate and ground would increase to the detriment of the dynamic performance of the device.
Furthermore, the portion of the shield that is located on top of the drain region is defined, in the direction of the drain electrode, by a lithographic process, and consequently its lateral extension cannot be controlled accurately. Since, as the working voltage of the device decreases, it is advantageous to reduce the lateral extension of the drain semiconductor region, which is only slightly doped, the horizontal extension of the shield towards the drain metal electrode sets constraints on an efficient reduction of the operating voltage.
Moreover, in the devices of the type considered, there exists the problem of reducing the source parasitic resistance due to the relatively high resistivity of the epitaxial layer that is less doped than the substrate.
According to U.S. Pat. No. 5,155,563, in order to reduce the source parasitic resistance, an enriched region is provided, which extends throughout the depth of the epitaxial layer and reduces the resistance thereof. To obtain diffusion of the dopant to depths sufficient to significantly alter the concentration of the epitaxial layer, so as to bring the minimum concentration of dopant to values higher than approximately 1017 atoms/cm3, it is necessary to use thermal processes for long periods of time and at high temperatures (T˜1150° C. for some hours). In a radio-frequency application, where the device has to stand up to drain voltages of about 70 V, it is necessary for the thickness of the epitaxial layer, at the end of all the thermal processes, not to drop below a few microns. The thickness of the epitaxial layer has a bearing both on the breakdown voltage of the device (Bvdss) and on the capacitance Cds between the drain regions and the underlying semiconductor region that has a doping of an opposite type and is at the lowest potential (ground) and connected to the source. In particular, the capacitance Cds, in particular when the drain electrode is positively biased, may be conveniently reduced by increasing the thickness of the epitaxial layer. Since the substrate contributes to the source resistance, it is not very resistive, and its dopant concentration is unlikely lower than 1018 atoms/cm3. In these conditions, the thermal process necessary for a dopant species implanted on the surface, such as for example, boron, to sufficiently raise the dopant concentration in a direction of the substrate is quite high. The effect of the diffusion process would not be limited to just the species implanted on the surface but would also involve the substrate, which would diffuse uniformly upwards in the direction of the epitaxial layer, where the concentration is low and is in the region of 1015 atoms/cm3. To prevent the epitaxial thickness from being reduced excessively it is necessary to grow an initial semiconductor layer, which can be up to approximately three times greater than the final one. The overall result is that the minimum dopant concentration between the surface and the “deep” substrate unlikely exceeds a concentration of 1017 atoms/cm3. Furthermore, since the final thickness of the epitaxial layer is a fraction of the initial one, any possibly absolute error in the growth stage would be amplified in relation to the smaller final residual thickness, negatively affecting the statistical reproducibility of the depth of the high-resistivity area. The diffusion upwards of the substrate in particular produces a dopant profile that decreases slowly from the substrate towards the surface, and consequently it is difficult to find a satisfactory compromise between breakdown voltage of the MOS, drain/source capacitance Cds, and parasitic resistance of the P+ type connection.
Alternatively, it is possible to employ more complex processes (see, for example, U.S. Pat. Nos. 5,869,875, 5,949,104 and 6,048,772), which, even though, in some cases, they have smaller horizontal dimensions, require opening of a trench, a process of doping, filling with a conductive material, and planarization of the surface. In the case of U.S. Pat. No. 6,048,772, the process of planarization is particularly difficult in view of the fact that the depth of the trench can exceed 2 μm.
Even more complex solutions (U.S. Pat. No. 6,034,415) envisage forming a conductive plug that extends through the entire thickness of the substrate to reach an enriched semiconductor area. The fabrication of the conductive plug involves a complicated photolithographic process that is carried out on the rear surface of the substrate and digging of a trench, which has a depth comparable with the thickness of the substrate.
For problems of thermal dissipation it is convenient to reduce to a minimum the vertical thickness of the device, compatibly with the technological limits imposed by the thickness reduction process, which is frequently linked to the brittleness of the semiconductor wafers. In these conditions, it is extremely difficult to perform a photolithographic process and etching on the rear surface of the wafer and to form a conductive plug. Furthermore, assuming that it is possible to obviate the problems of brittleness and assuming that the final thickness of the device may reach small values in the region of 50 μm, nevertheless particularly burdensome etching processes are involved.